1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. One technique used to form STI structures initially involves growing a pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layer are patterned. Then, an etching process is performed to form trenches in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process is performed to overfill the trenches with an insulating material such as silicon dioxide. A chemical mechanical polishing (CMP) process is then performed using the pad nitride layer as a polish-stop layer to remove the excess insulation material. Then, a subsequent deglazing (etching) process may be performed to insure that the insulating material is removed from the surface of the pad nitride layer. This deglaze process removes some of the STI structures.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. As a result, the STI structures may not perform their isolation function as intended which may result in problems such as increased leakage currents, etc. Furthermore, since the erosion of the STI structures is not uniform across a die or a wafer, such structures may have differing heights, which can lead to problems in subsequent processing operations. For example, such height differences may lead to uneven surfaces on subsequently deposited layers of material which may require additional polishing time in an attempt to planarize the surface of such layers. Such additional polishing may lead to the formation of additional particle defects which may reduce device yields.
The present disclosure is directed to various methods of forming epitaxially formed layers of material and semiconductor devices incorporating such layers of material that may at least reduce or eliminate one or more of the problems identified above.